1. Field of the Invention:
The present invention relates to an insulated gate field effect transistor having a DMOS structure and utilized as a power switching device which can withstand high voltage and allow large current to flow, and to a manufacturing method of the same. Such an insulated gate field effect transistor is suitably used for a vehicule ignition apparatus and a motor driving inverter.
2. Discussion of Related Art:
It is known that an insulated gate bipolar transistor ("IGBT")enables high withstand voltage compatible with low ON resistance. Although the IGBT has a similar structure to a power MOSFET, the IGBT has a layer of an opposite electrical conductivity type from a source layer as a drain region.
FIG. 19A shows a top schematic view of the main part of an unit cell of the IGBT and FIG. 19B shows a sectional view of the IGBT taken along a line 19B--19B in FIG. 19A. The structure of the IGBT will be explained below based on FIGS. 19A and 19B. What an N.sup.- type epitaxial layer 2 is grown on the surface of a P.sup.+ type substrate 1 is used as a substrate of the IGBT. Then, a deep P.sup.+ type diffusion layer (a "deep P well") 3 of which concentration is relatively high and a P type diffusion layer (a "channel P well") 4 of which concentration is lower than that of the deep P well 3 are formed in the surface of the N.sup.- type epitaxial layer 2.
An emitter region 5 composed of an N.sup.+ type diffusion layer (corresponding to a source region of a power MOSFET) is formed in the surfaces of the deep P well 3 and the channel P well 4. Further, a gate electrode 7 is provided on the channel P well 4 with a gate oxide film 6a interposed. The gate electrode 7 is formed to have a pattern indicated by the hatched portion in FIG. 19A. The gate electrode 7 is covered by an interlayer insulating film 6b. A contact hole (a part surrounded by a dotted line in FIG. 19A) is formed through the gate oxide film 6a and the interlayer insulating film 6b. An emitter electrode 8 is disposed to contact the emitter region via this contact hole. A collector electrode 9 is disposed on the back of the P.sup.+ type substrate.
FIG. 20 is a partially sectional view of the IGBT to describe the operation thereof when the IGBT thus constructed is actually operated. The operation of the IGBT will be explained based on FIG. 20.
When a certain threshold voltage is applied to the gate electrode 7, the surface of the channel P well 4 below the gate electrode 7 is inverted, thus creating an electron channel. Then, electrons flow into the N.sup.- type epitaxial layer 2 through this channel. The electrons which have flown into the N.sup.- type epitaxial layer 2 drop the potential of the N.sup.- type epitaxial layer 2 so as to forwardly bias the PN junction between the P.sup.+ type substrate 1 and the N.sup.- type epitaxial layer 2. As a result, holes which are a minority carrier flow from the P.sup.+ type substrate 1 to the N.sup.- type epitaxial layer 2. Due to the flow of the holes, the N.sup.- type epitaxial layer 2 is subjected to modulation of the electrical conductivity, thereby considerably reducing its resistivity. As a result, a large hole current flows from the collector electrode 9 to the emitter electrode 8.
Because the horizontal resistance of the channel P well 4 (the part indicated by a mark of resistance in FIG. 20) is large, a large voltage drop occurs in the channel P well 4. When the internal resistance of the channel P well 4 is taken into account, the electrical connection in the IGBT may be expressed by a circuit diagram as shown in FIG. 21.
That is, an FET shown in FIG. 21 is composed of the gate electrode 7, the channel P well 4, the emitter region 5 and the N.sup.- type epitaxial layer 2, a PNP transistor is composed of the P type substrate 1, the N.sup.- type epitaxial layer 2, and the channel P well 4 and the deep P well 3, and an NPN transistor (a "parasitic transistor") is composed of the emitter region 5, the channel P well 4 and the N.sup.- type epitaxial layer 2. A resistance R denotes the internal resistance of the channel P well 4.
When the quantity of the hole current flowing through the resistance R increases as shown in FIG. 21, the large voltage drop occurs at the resistance R. Then, when this voltage drop reaches a value which can forwardly bias the PN junction of the emitter region 5 and the channel P well 4, the parasitic transistor turns on. Thereby, a so-called latch-up phenomenon occurs, by which the IGBT is kept continuously conductive state.
FIG. 22 shows the state of the flow of the holes in the IGBT on the top surface of a wafer. Most of the holes injected from the P.sup.+ type substrate 1 to the N.sup.- type epitaxial layer 2 flow upward in the N.sup.- type epitaxial layer 2 and reach the emitter electrode 8 passing through the channel P well 4 which is located at the upper part thereof. However, the holes injected to the N.sup.- type epitaxial layer 2 at the periphery of a cell region in which the current flows via the channel flow heading toward the nearby cell region and reach the emitter electrode 8 because no cell region is formed thereabove. Because the flows of holes from the periphery are thus concentrated at the edge portion of the cell region as a result, its density becomes higher than that of the hole current flowing through the inner part of the cell region. That is, the flow rate of the holes increases in the vicinity of the edge portion of the cell region. Therefore, there has been a problem that the voltage drop due to the horizontal resistance of the channel P well 4 in the vicinity of the cell edge portion becomes large and the above-mentioned latch-up phenomenon readily occurs.
The present invention is intended to solve the aforementioned problem and its object is to improve the ruggedness against the latch-up phenomenon by relieving the concentration of the holes at the cell region in the vicinity of the cell edge portion.